Subject: [Ace] WebEx meeting info: How to Select Hardware for IoT Systems?

From: Hannes Tschofenig <[email-masked]>
Date: Thu, 11 Sep 2014 16:37:39 +0200

Hi all,

here is the webex information for our conference call tomorrow.
We am looking forward to an interesting discussion.

Ciao
Hannes & Kepeng

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*How to Select Hardware for IoT Systems?*
Friday, September 12, 2014
1:00 pm  |  GMT Summer Time (London, GMT+01:00)  |  1 hr

Join WebEx meeting
https://ietf.webex.com/ietf/j.php?MTID=m1b9d0bcee385ebb169b4fb5631b7ab53

Meeting number: 	642 573 373
Meeting password: 	foobar

Join by phone:
+1-877-668-4493* Call-in toll free number (US/Canada)
+1-650-479-3208* Call-in toll number (US/Canada)
Access code: 642 573 373

Toll-free calling restrictions:
http://www.webex.com/pdf/tollfree_restrictions.pdf

Add this meeting to your calendar:
https://ietf.webex.com/ietf/j.php?MTID=m5e23b4523c843310775c5e9c55f2f8e4

Can't join the meeting? Contact support:
https://ietf.webex.com/ietf/mc

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From: Rene Struik <[email-masked]>
Date: Fri, 12 Sep 2014 17:51:20 -0400

Hi Hannes:

Thanks for facilitating the ARM call.

Please find below some notes that I wrote down based on the ARM 
presentation by Peter Aldworth (I had to leave the call at 9:05am EDT 
and do not know whether it ran longer).
{Note: based on notes, since no access to presentation slides material 
(yet)}

Notes:
* silicon area is only tiny portion of hardware bill of material cost; 
indirect cost, such as code density, much more important
* lifetime cost, such as battery lifetime and capability of, e.g., 
upgrading the device, much more important
* development and deployment cost could be lowered by code reuse and 
debugging, etc., tools are nice to have, but for huge quantities again 
amortized cost relatively low
* per-device MCU prices {with 128-256kB programming memory; 16kB-32kB 
SRAM} in the market (with low volume) seem to favor 32-bit processors
   (8-bit: $3.40-$9; 16-bit: $3-$40; 32-bit: $1.80-$9) -- extremely wide 
range in price points, but many vendors in ecosystem
* cost of crypto processor [f/u. question Ludwig Seitz]: hardware-assist 
reduces code footprint, since functionality in hardware; no significant 
increase in cost at all
* power consumption significantly benefits from crypto acceleration in 
hardware (e.g., less memory access)
* energy cost [f/u. question Dan Romascanu]: various mechanisms to 
reduce energy during sleep mode (e.g. just SRAM, clock alive; processor 
does not run,, etc.
* RAM cost [f/u. question Dominique Barthel]: RAM cost far less 
important than cost of # PINs, volume
* Generally, perceived as mistake to optimize on cost

Tentative conclusions, based on these  notes, for ACE-related discussions:
* potential need to reconsider relevance of device classes that have 
popped up in some device capability discussions in the past (including 
SRAM cost)
* inclusion of crypto accelerator has barely impact on overall cost 
(including generic multiplier)
* focus should be on total lifecycle cost and functionality offered 
(provisioning, upgrade, etc.)
* need more detail on energy consumption crypto operations (and, 
perhaps, time latencies)

Overall, presentation seems to suggest one can view all crypto building 
blocks as commodities for IoT security architectural deliberations with 
IETF ACE.

On 9/11/2014 10:37 AM, Hannes Tschofenig wrote:
> _______________________________________________
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