Subject: Lucent pending actions

From: "Daniel Feldman" <[email-masked]>
Date: Tue, 2 Jul 2002 23:22:37 +0200

Hello Douglas,
	I would like to continue my answers on the Lucent pending
actions:

Q: Daniel: Check again feasibility of adding Ethernet both in the
Backplane and the Network
A: TXC's Estream 2 (previously called CellMAC GE) is the appropriate
device to interface with (c)X-cess. It includes IPoEthernet, VLAN,
etc... and it has a PoS-PHY L2/3 interface. Please ask Nick
Taluja/Hoshang Mulla for more info (i.e. specs & availability -- they
have offered this device to Ericsson). This means that we do not have
internal support for Ethernet in the current version of (c)X-cess, but
this is planned as part of the next revision of the chip.

Q:Daniel: CDMA-2000 Worst-case average packet size is 20 bytes, instead
of 32 bytes. However, PPPmux is assumed to multiplex packets and make
them into a 300 bytes packets. We need to analyze how the chip copes
with this kind of requirement, how many SDRAM’s are needed Send answer
to them
A: Elazar/Yosi/Nir are still checking
Q: Daniel: Send description of our PCR/PBR shaping. SCR/SBR is a hard
requirement, so they want to check our PCR/PBR implementation.
A: Our PBR/PCR shaper is a HW implementation of Token Bucket. Please see
the description of the algorithm in the attached file (Annex A of ITU-T
Y.1221). Our maximum burst size is 1700 bytes (for PPPoHDLC) and our
granularity for scheduling is 128 clock cycles, i.e., our scheduler can
support sustained scheduling of 16-bytes packets. For SCR/SBR shaping we
would have to implement Dual-Leaky bucket. This would mean an addition
of 112Kbit internal SRAM and 60Kgates, plus the development work itself.
We need to know how critical this feature is for Lucent. Maybe we can
negotiate adopting it for an LOI and extra time.
 <<RP-020108.pdf>> 

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Daniel Feldman
System Architecture Group Manager, IC4IC Ltd.
office:   +972(4)959-4644 ext. 121
mobile: +972(55)99-0299
fax:      +972(4)959-4944
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